The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device for forming, for example, a memory circuit by using MOS FETs.
The semiconductor devices shown in FIGS. 1 to 3 are already known, as disclosed in Japanese Patent Publication No. 56-3688. FIG. 1 shows a plan view of a part of the semiconductor device; FIG. 2 is an equivalent circuit of the semiconductor device; and FIG. 3 is a cross sectional view taken along line III--III in FIG. 1.
As shown in FIGS. 1 to 3, a gate insulating film 12 and a gate electrode 14 are formed in the semiconductor device on a P type semiconductor substrate 10. An N.sup.+ region 16 is formed between gate electrodes by the diffusion process. In the circuit shown in FIG. 1, MOS transistors Q11, Q21 and Q31 and MOS transistors Q12, Q22 and Q32 are connected in series. The load transistors are not shown.
The number of gates provided in the semiconductor devices depend on the specification given by a user. For example, in order to render the MOS transistor Q22 nonoperative and reduce the input terminals by one, the source and drain of the MOS transistor Q22 are shorted by means of an ion implanted layer 18.
The prior semiconductor devices are fabricated by the manufacturing process, as shown in FIGS. 4A to 4E. According to the manufacturing process, however, the process of the ion implantation as mentioned above is performed at the initial stage of the wafer process. This leads to a delay in the appointed date of delivery.
A manufacturing method of a prior semiconductor device will be described referring to FIGS. 4A to 4E. As shown in FIG. 4A, a field oxide film 24 of 8,000 to 15,000 .ANG. in thickness is formed over a P type semiconductor substrate 10, as shown in FIG. 4A. Next, a field oxide film 24 on the active region in which elements are formed is removed. At this portion, an SiO.sub.2 film 26 for the gate oxide film of 500 to 1,000 .ANG. is formed by the thermal oxidizing process. With a photoresist mask on the surface of the semiproduct, N type impurity ions are implanted into a portion of the semiproduct where a channel of a depletion type MOS transistor is formed, thereby forming N type impurity regions 28a to 28c. The depletion type MOS transistors are used as a load MOS transistor QO serving as a drive section of an inverter, and also as elements Q2 and Qn-1 for storing "0" in the memory region. The N type impurity region 28a is used for the load MOS transistor and the regions 28b and 28c are used for the depletion type in the driver (memory) MOS transistors. Data is stored by rendering given elements, such as Q2 and Qn-1, into depletion type in accordance with the memory contents. Where in the memory region N type impurity for forming the depletion type elements is implanted is determined by the customer's order. A mask exclusively used for this implantation is prepared.
A polysilicon layer for the gate electrode of 3,000 to 4,000 .ANG. in thickness is then deposited on the SiO.sub.2 film 26. The gate of the load MOS transistor QO of the drive section is shorted to its source in a buried contact manner, as shown in FIG. 4B. This is realized by removing in advance a part of the SiO.sub.2 oxide film 26 on the region where the source of the load transistor QO is formed and then depositing polysilicon. After patterning the polysilicon layer by a photoengraving process, the SiO.sub.2 film 26 is etched away with a mask of the polysilicon layer, thereby forming gate oxide films 12.sub.0 to 12.sub.n and gate electrodes 14.sub.0 to 14.sub.n. In the next step, with a mask of the gate electrodes 12.sub.0 to 12.sub.n, N type impurity is diffused into the semiproduct to form the drain regions 30.sub.0 to 30.sub.n and the source regions 32.sub.0 to 32.sub.n of MOS transistors Q0 to Qn. Because the load MOS transistor Q0 and the predetermined transistors Q2 and Qn-1 of the driver MOS transistors have N type ions injected into the channel region between the source and drain in the step mentioned above, they are depletion type transistors. The remaining transistors are of the enhancement type (FIG. 4B).
An SiO.sub.2 film 34 of 2,000 to 6,000 .ANG. is formed on a semiconductor substrate 10 as a protective film, as shown in FIG. 4C. Contact holes 36 for interconnection wirings are formed by the photoengraving process on the drain region 30.sub.0, on the source region 32.sub.0 of the load MOS transistor Q0, and on the source region 32.sub.n of the transistor Qn.
As shown in FIG. 4D, a surface smoothing layer 38 of the 5,000 to 7,000 .ANG. thickness is deposited on the semiconductor substrate. To form the contact holes 36 for wiring, the surface smoothing layer 38 is etched. As shown in FIG. 4E, aluminum is vapor-deposited and etched to form a V.sub.DD power source electrode 40, an output electrode 42 and a V.sub.SS electrode 44. A protective film is then formed over the entire surface and bonding pads to exterior are formed thereon. At this stage, the chip fabrication process is completed.
The operation of a semiconductor device formed through the steps mentioned above will be described. The semiconductor device produces the contents of the selected transistor at the output electrode 42 in response to the select signal to the gate electrodes 14.sub.1 to 14.sub.n of the driver MOS transistors Q1 to Qn. When the transistor Q1 is selected and only the gate electrode 14.sub.1 is at low potential, the circuit is electrically cut off by the transistor Q1 because this transistor is of the enhancement type. Accordingly, the output signal is at the power source potential. This means that logic "1" has been stored in the transistor Q1. When the transistor Q2 is selected, and only the gate electrode 14.sub.2 is at low potential, i.e. about 0 V, the transistor Q2 has a shortcircuit between the source and drain because this transistor is of the depletion type. Accordingly, the conductive state of the circuit is maintained and never electrically cut off. Accordingly, the output signal is at low potential. This means that logic "0" has been stored in the transistor Q2. In this way, data are stored in the memory region by forming the MOS transistors Q1 to Qn into two types, the enhancement type and the depletion type.
In the prior manufacturing method, the impurity implantation into the channel region for forming the depletion type MOS transistor in the memory region is performed at the initial stage in the entire manufacturing process. The determination of which transistor should be of a depletion type depends on the type of the data to be stored. Actually, after the mask pattern is determined by a customer's order, the ion implantation is performed. Various process steps such as impurity diffusing step for forming the source and drain are subsequently performed before the semiconductor device is completed. Therefore, it is time-consuming to manufacture and deliver semiconductor products according to a customer's order. In this respect, the manufactures have not fully satisfied to the customer's demand.
Proposals to cope with this problem are disclosed in U.S. Pat. No. 4,080,718 and Japanese laid-open patent application No. 53-75781. In these proposals, impurity is introduced into the channel region by the ion-implantation in the final stage, in order to render the MOS transistor into a deletion type.
In the final step, a PSG layer or a CVD layer is etched and impurity is then introduced into the semiconductor substrate by the ion-implantation process. The semiconductor device thus fabricated is delivered as is. Accordingly, its reliability is poor.
When the PSG layer and the CVD layer on the gate electrode are removed for making an ion-implantation, the Al interconnection wiring is not located on the gate electrodes to be opened. This state will be described referring to FIGS. 5 and 6. FIG. 5 shows a plan view of the semiconductor device and FIG. 6 is a cross sectional view taken along line VI--VI in FIG. 5. A gate electrode 14 is formed on the semiconductor substrate 10, with a gate insulating film 12 disposed therebetween. An N type impurity region 28, which will be the source, and drain regions are formed on both sides of the gate electrode 14. An Al interconnection wiring 52 is formed orthogonal to the gate electrode 14. In order to short the source and drain of one MOS transistor, the region 50 must be opened. In this case, care must be taken so as to etch away the Al wiring 52 on the field oxide film 24. Accordingly, the MOS transistor and the Al wiring 52 must be disposed separately. As a result, the integration density is correspondingly reduced.